DIGITAL ELECTRONICS VIRTUAL LAB

16:1 Multiplexer (16-to-1 MUX) Experiment

Simulation Active

Hierarchical Gate-Level Circuit (4-Stage 2:1 MUX Tree)

Shows 15 smaller 2:1 MUXes connected in 4 stages to form a 16:1 Multiplexer

Active Signal Path Logic 1 (High) Logic 0 (Low)
Level 1 (S0) selects adjacent inputs → Level 2 (S1) combines 4 outputs → Level 3 (S2) combines 2 outputs → Level 4 (S3) produces Y.

Truth / Selection Table

16-to-1 Multiplexer Selection Mapping
Click row to set Select Lines
Decimal S3 S2 S1 S0 Selected Input Input Value Output Y

Educational Guide & Technical Reference

THEORY & PRINCIPLES

What is a 16:1 Multiplexer?

A 16:1 Multiplexer (MUX), also known as a data selector, is a combinational digital logic circuit that accepts 16 digital data inputs (I0 through I15) and routes exactly one selected input to a single output line (Y) based on a 4-bit select code (S3, S2, S1, S0).

Y = m0·I0 + m1·I1 + ... + m15·I15

Why are 4 Select Lines Required?

To uniquely identify and address 16 distinct data channels, a binary addressing scheme requires N select lines such that 2N ≥ 16. Since 24 = 16, exactly 4 select lines (S3, S2, S1, S0) are needed.

Multiplexer Scaling Hierarchy

The general relationship between the number of data inputs (N) and required select lines (S) is given by:

Select Lines (S) = log2(N)     Data Inputs (N) = 2S
MUX Type Data Inputs (N) Select Lines (S = log2 N) Number of 2:1 MUXes needed
2:1 MUX2 (I0–I1)1 (S0)1
4:1 MUX4 (I0–I3)2 (S1, S0)3 (2 + 1)
8:1 MUX8 (I0–I7)3 (S2, S1, S0)7 (4 + 2 + 1)
16:1 MUX16 (I0–I15)4 (S3, S2, S1, S0)15 (8 + 4 + 2 + 1)

Hierarchical MUX Tree Breakdown

A 16:1 Multiplexer can be synthesized using a tree of fifteen 2:1 Multiplexers organized into 4 distinct cascade stages:

  • Level 1 (Stage 1 - 8 MUXes: M0 to M7): Controlled by LSB S0. Selects between adjacent inputs (I0, I1), (I2, I3), ..., (I14, I15).
  • Level 2 (Stage 2 - 4 MUXes: M8 to M11): Controlled by S1. Combines outputs of Level 1 into 4 intermediate signals.
  • Level 3 (Stage 3 - 2 MUXes: M12, M13): Controlled by S2. Combines outputs of Level 2 into 2 intermediate signals.
  • Level 4 (Stage 4 - 1 MUX: Output Y): Controlled by MSB S3. Performs final 2-to-1 selection to produce output Y.

Practical Engineering Applications

CPU Data Routing

Used in ALU and register files to route data from 1 of 16 registers to internal buses.

Digital Communication

Time Division Multiplexing (TDM) to transmit 16 distinct signal channels over a single shared transmission medium.

Data Acquisition Systems

Sequentially samples 16 analog sensors into a single Analog-to-Digital Converter (ADC).

Boolean Logic Synthesis

Implements any arbitrary 4-variable or 5-variable Boolean logic function without discrete logic gates.